In connection with storage of data, a method has been proposed in which data can be written in and read out in bit-parallel relation of N bits from independently operable N=2.sup.n.sbsp.1 memories in the row direction and column direction and in which, when the data reduction rate is an exponential power of 2, reduced data can be written in and read out from the N memories in bit-parallel relation of 2.sup.n.sbsp.1 bits in the row direction and column direction. The proposed method is such that all the data are divided into blocks each including 2.sup.n.sbsp.1.sup.+n.sbsp.2 bits in the row direction and 2.sup.n.sbsp.1.sup.+n.sbsp.2 bits in the column direction, where 2.sup.n.sbsp.2 is the maximum data reduction rate, and each of the blocks composed of 2.sup.n.sbsp.1.sup.+n.sbsp.2 .times.2.sup.n.sbsp.1.sup.+n.sbsp.2 bits is used as a unit to be processed. According to the proposed method, the data are allocated to the N memories capable of making independent parallel operation so that the data in each of individual groups may not be allocated to the same memory when the results of sampling of the data in the same row and same column in the block at a bit interval of 2.sup.h (0.ltoreq.h.ltoreq.n.sub.2) are grouped into groups of N bits.
To explain the above method in which all the data in the individual groups can be allocated to the different memories when the results of sampling of the data in the same row and same column in the block at the bit interval of 2.sup.h (0.ltoreq.h.ltoreq.n.sub.2) are grouped into the groups of N=2.sup.n.sbsp.1 bits, suppose, for example, the case where N=8 and n.sub.2 =1. According to the proposed method, the former 8 bits of the data in an i-th row (i=1-8) in the block are subjected to an (i-1)-bit cyclic shift to be stored at an address (32k.sub.0 +i-1) in the memories m.sub.1 to m.sub.8 respectively; the latter 8 bits of the data in the i-th row (i=i-8) are subjected to an i-bit cyclic shift to be stored at an address (32k.sub.0 +i+7) in the respective memories m.sub.1 to m.sub.8 ; the former 8 bits of the data in an i-th row (i=9-16) are subjected to an (i-8)-bit cyclic shift to be stored at an address (32k.sub.0 +i+7) in the respective memories m.sub.1 to m.sub.8 ; and the latter 8 bits of the data in the i-th row (i=9-16) are subjected to an (i-7)-bit cyclic shift to be stored at an address (32k.sub.0 +i+15) in the respective memories m.sub.1 to m.sub.8. FIG. 1 shows the numbered data of 16.times.16 bits, and FIG. 2 shows that the data shown in FIG. 1 are allocated to and stored at the individual addresses in the memories m.sub.1 to m.sub.8 according to the proposed method.
FIG. 3 shows the less-significant address values applied to the memories m.sub.1 to m.sub.8 during data writing and reading in the column direction when the data are allocated to the memories in the manner shown in FIG. 2. It will be apparent from FIG. 3 that 1 is added to the less-significant address values during data writing and reading in the column direction. (For example, when i (0.ltoreq.i.ltoreq.7) is the less-significant address value applied to the memory m.sub.1, a less-significant address value given by the remainder of division of (i+j-1) by 8 is applied to a memory m.sub.j. The same applies also to the reading of data with a data reduction rate of 1/2. Thus, in the proposed method, the addresses applied to the memories must be converted by processing in the manner above described. Therefore, the prior art method is defective in that the scale of the address conversion processing circuit increases in proportion to the number N of the memories.